| 2012 |
Efficient Mapping of Task Graphs onto Reconfigurable Hardware Using Architectural Variants |
M. Huang, V. K. Narayana, M. Bakhouya, J. Gaber and T. El-Ghazawi |
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| 2012 |
OpenCL and the 13 Dwarfs: A Work in Progress |
W. Feng, H. Lin, T. Scogland, J. Zhang |
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| 2012 |
FPGA-Accelerated Isotope Pattern Calculator for Use in Simulated Mass Spectrometry Peptide and Protein Chemistry |
C. Pascoe, D. Box, H. Lam, and A. George |
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| 2012 |
A Framework to Analyze, Compare, and Optimize High-Performance, On-Board Processing Systems |
N. Wulf, A. George, and A. Gordon-Ross |
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| 2012 |
Performance Analysis of GPU Accelerators with Realizable Utilization of Computational Density |
J. Richardson, A. George, and H. Lam |
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| 2012 |
Energy Budgeting for CubeSats with an Integrated FPGA |
S. Arnold, R. Nuzzaci, J. Antoon, and A. Gordon-Ross |
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| 2012 |
Accelerated High-Performance Computing Through Efficient Multi-Process GPUResource Sharing |
T. Li, V. K. Narayana and T. El-Ghazawi |
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| 2012 |
VirtualRC: A Virtual FPGA Platform for Applications and Tools Portability |
R. Kirchgessner, G. Stitt, A. George, and H. Lam |
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| 2012 |
Automatic NUMA Characterization using Cbench |
R. Braithwaite, W. Feng, P. McCormick |
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| 2012 |
Reliability of a Softcore Processor in a Commercial SRAM-Based FPGA |
N. Rollins and M. Wirthlin |
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| 2012 |
A Comparison Study on Implementing Optical Flow and Digital Communications on FPGAs and GPUs |
J. Bodily, B. Nelson, Z. Wei, D. Lee, J. Chase |
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| 2012 |
Lost in Translation: Challenges in Automating CUDA-to-OpenCL Translation |
P. Sathre, M. Gardner, W. Feng |
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| 2012 |
An Introduction to TSHMEM for Shared-Memory Parallel Computing on Tilera Many-Core Processors |
B. Lam, A. George, and H. Lam |
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| 2012 |
Bandwidth-Sensitivity-Aware Arbitration for FPGAs |
L. Hao, G. Stitt |
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| 2012 |
BPR: Fast FPGA Placement and Routing using Macroblocks |
J. Coole and G. Stitt |
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| 2012 |
A Design Assembly Framework for FPGA Back-End Acceleration |
T. Frangieh, P. Athanas |
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| 2012 |
A Low-overhead Interconnect Architecture for Virtual Reconfigurable Fabrics |
A. Landy and G. Stitt |
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| 2012 |
Radiation Testing of FPGA-Based High-Speed Serial Communication |
K. Ellsworth, A. Harding, C. Ballew, T. Haroldsen, M. Wirthlin, and B. Nelson |
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| 2012 |
Reliability Models for SEC/DED Memory with Scrubbing in FPGA-based Designs |
Y. Li, B. Nelson, and M. Wirthlin |
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| 2012 |
Scrubbing Optimization via Availability Prediction (SOAP) for Reconfigurable Space Computing |
Q. Martin and A. George |
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| 2012 |
Overhead and Reliability Analysis of Algorithm-Based Fault Tolerance in FPGA Systems |
A. Jacobs, G. Cieslewski, and A. George |
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| 2012 |
RCML: An Environment for Estimation Modeling of Reconfigurable Computing Systems |
C. Reardon, B. Holland, A. George, G. Stitt, and H. Lam |
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| 2012 |
FPGA-based Reconfigurable Computing for Pricing Multi-asset Barrier Options |
R. Sridharan, G. Cooke, K. Hill, H. Lam, and A. George |
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| 2011 |
Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation |
Greg Stitt, James Coole |
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| 2011 |
Reduced-Precision Redundancy on FPGAs |
B. Pratt, M. Fuller, and M. Wirthlin |
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| 2011 |
Communication Visualization for Bottleneck Detection of High-Level Synthesis Applications |
J. Curreri, G. Stitt, and A. George |
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| 2011 |
Hardware Module Reuse and Runtime Assembly for Dynamic Management of Reconfigurable Resources |
A. Jara-Berrocal and A. Gordon-Ross |
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| 2011 |
Partially Reconfigurable System-on-Chips for Adaptive Fault Tolerance |
S. Yousuf and A. Gordon-Ross |
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| 2011 |
A Static Task Scheduling Framework for Independent Tasks Accelerated using a Shared Graphics Processing Unit |
T. Li, V. K. Narayana and T. El-Ghazawi |
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| 2011 |
Formulation-level Design Space Exploration for Partially Reconfigurable FPGAs |
R. Kumar and A. Gordon-Ross |
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| 2011 |
Reflex Barrier: A Scalable Network-Based Synchronization Barrier |
A. Anbar, O. Serres and T. El-Ghazawi |
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| 2011 |
Spectral Method Characterization of FPGA and GPU Accelerators |
K. Pereira, P. Athanas, H. Lin, and W. Feng |
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| 2011 |
StreamMR: An Optimized MapReduce Framework for AMD GPUs |
M. Elteir, H.Lin, W. Feng, T. Scogland |
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| 2011 |
An Architecture for Reconfigurable Multi-core Explorations |
O. Serres, V.K. Narayana and T. El-Ghazawi |
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| 2011 |
Novo-G: At the Forefront of Scalable Reconfigurable Computing |
A. George, H. Lam, and G. Stitt |
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| 2011 |
Performance Characterization and Optimization of Atomic Operations on AMD GPUs |
M. Elteir, H. Lin, and W. Feng |
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| 2011 |
Dual Channel Architecture for Reliable FPGA high Speed Serial Links |
K. Ellsworth, T. Haroldsen, B. Nelson, and M. Wirthlin |
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| 2011 |
An Integrated Development Toolset and Implementation Methodology for Partially Reconfigurable System-on-Chips |
A. Jara-Berrocal and A. Gordon-Ross |
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| 2011 |
RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs |
C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson and B. Hutchings |
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| 2011 |
XDL-Based Module Generators for Rapid FPGA Design Implementation |
S. Ghosh and B. Nelson |
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| 2011 |
Platform-Aware Bottleneck Detection for Reconfigurable Computing Applications |
S. Koehler, G. Stitt, and A. George |
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| 2011 |
An Analytical Model for Multi-Level Performance Prediction of Multi-FPGA Systems |
B. Holland, A. George, H. Lam, and M. Smith |
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| 2011 |
SHMEM+: A Multilevel-PGAS Programming Model for Reconfigurable Supercomputing |
V. Aggarwal, A. George, C. Yoon, K. Yalamanchili, and H. Lam |
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| 2011 |
An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing |
G. Stitt, A. George, H. Lam, M. Smith, V. Aggarwal, G. Wang, C. Reardon, B. Holland, S. Koehler, and J. Coole |
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| 2011 |
On the Efficacy of a Fused CPU+GPU Processor for Parallel Computing |
M. Daga, A. Aji, and W. Feng |
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| 2011 |
Address translation optimization for Unified Parallel C multi-dimensional arrays |
O. Serres, A. Anbar, S. G. Merchant, A. Kayi and T. El-Ghazawi |
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| 2011 |
HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping |
C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson, and B. Hutchings |
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| 2011 |
Architecture-Aware Mapping and Optimization on a 1600-Core GPU |
M. Daga, T. Scogland, W. Feng |
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| 2011 |
SCIPS: An Emulation Methodology for Fault Injection in Processor Caches |
N. Wulf, G. Cieslewski, A. Gordon-Ross, and A. George |
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| 2011 |
Experiences with UPC on TILE-64 processor |
O. Serres, A. Anbar, S. Merchant and T. El-Ghazawi |
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