| 2017 |
A Test Bed Study of Network Determinism for Heterogeneous Traffic Using Time-Triggered Etherne |
A. Starke, M. Ford, D. Kumar, J. McNair, A. Bell |
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| 2017 |
Overlay-based side-channel countermeasures: A case study on correlated noise generation |
A. Baylis, G. Stitt, and A. Gordon-Ross |
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| 2017 |
A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance |
D. Wilson, A. Shastri, and G. Stitt. |
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| 2017 |
Exploration of TMR Fault Masking with Persistent Threads on Tegra GPU SoCs |
A. Milluzzi, A. George, |
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| 2017 |
A scalable, low-overhead finite-state machine overlay for rapid FPGA application development |
D. Wilson and G. Stitt, |
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| 2017 |
Optimizing FPGA Performance, Power, and Dependability with Linear Programming |
N. Wulf, A. George, A. Gordon-Ross |
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| 2017 |
AutoMatch: An Automated Framework for Relative Performance Estimation and Workload Distribution on Heterogeneous HPC Systems |
A. Helal, W. Feng, C. Jung, Y. Hanafy |
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| 2016 |
A Research Platform for Custom Memory Cube |
G. Wang, H. Lam, Y. Zou, R. Xavier, S. Gundecha, A. George |
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| 2016 |
Analysis of Fixed, Reconfigurable, and Hybrid Devices with Computational, Memory, I/O, & Realizable-Utilization Metrics |
J. Richardson, K. Cheng, A. George, H. Lam |
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| 2016 |
A Framework for Evaluating and Optimizing FPGA-based SoCs for Aerospace Computing |
N. Wulf, A. George, A. Gordon-Ross |
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| 2016 |
Benefits of Complementary SEU Mitigation for the LEON3 Soft Processor on SRAM-Based FPGAs |
A. Keller, M. Wirthlin |
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| 2016 |
SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing |
M. Wirthlin, A. Keller, C. McCloskey, P. Ridd, D. Lee, J. Draper |
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| 2016 |
Configuration Prefetching and Reuse for Preemptive Hardware Multitasking on Partially Reconfigurable FPGAs |
A. Morales-Villanueva, R. Kumar, and A. Gordon-Ross |
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| 2016 |
HISC/R: An Efficient Hypersparse Storage Format for Scalable Graph Processing |
R. Kirchgessner, G. De La Torre, A. George, V. Gleyzer |
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| 2016 |
An OpenCL Framework for Distributed Apps on a Multidimensional Network of FPGAs |
Lawande, A. George, H. Lam |
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| 2016 |
Edit Real-Time, Low-Latency Image Processing with High Throughput on a Multi-Core SoC |
Ramesh, A. George, H. Lam |
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| 2016 |
A q-gram Birthmarking Approach to Predicting Reusable Hardware |
K. Zeng, P. Athanas |
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| 2016 |
Computational and Memory Analysis of Tegra SoCs |
Milluzzi, A. George, H. Lam |
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| 2016 |
Novo-G#: A Community Resource for Exploring Large-Scale Reconfigurable Computing with Direct and Programmable Interconnects |
George, M. Herbordt, H. Lam, A. Lawande, J. Sheng |
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| 2016 |
FPGA-Pipelined Discrete-Event Simulations for Accelerated Behavioral Emulation of Extreme-Scale Systems |
Pascoe, N. Kumar, K. Alli, H. Lam, G. Stitt, A. George |
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| 2016 |
μCSP: A Diminutive, Hybrid, Space Processor for Smart Modules and CubeSats |
Wilson, J. MacKinnon, P. Gauvin, S. Sabogal, A. George |
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| 2016 |
Behavioral Emulation for Scalable Design-Space Exploration of Algorithms and Architectures |
N. Kumar, C. Pascoe, C. Hajas, H. Lam, G. Stitt, A. George |
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| 2016 |
Novo-G#: a Multidimensional Torus-based Reconfigurable Cluster for Molecular Dynamics, |
A. Lawande, A. George, H. Lam |
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| 2016 |
A Methodology for Estimating Reliability of SmallSat Computers in Radiation Environments |
Wilson, A. George, B. Klamm |
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| 2016 |
DrSEUs: A Dynamic Robust Single-Event Upset Simulator |
Carlisle, N. Wulf, J. MacKinnon, A. George |
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| 2016 |
Packing a Modern Xilinx FPGA Using RapidSmith |
T. Haroldsen, B. Nelson, B. Hutchings |
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| 2016 |
Improving Compression Ratios for High Bit-Depth Grayscale Video Formats |
Ho, A. George, A. Gordon Ross |
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| 2015 |
Core-level modeling and frequency prediction for DSP applications on FPGAs |
G. Wang, G. Stitt, H. Lam, A. George |
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| 2015 |
On the Performance, Energy, and Power of Data-Access Methods in Heterogeneous Computing Systems |
R. Kalidas, M. Daga, K. Krommydas, W. Feng |
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| 2015 |
Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs |
A. Morales-Villanueva, A. Gordon-Ross |
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| 2015 |
An Automated High-level Design Framework for Partially Reconfigurable FPGAs |
R. Kumar and A. Gordon-Ross |
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| 2015 |
MACS: A Highly Customizable Low-latency Communication Architecture |
R. Kumar and A. Gordon-Ross |
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| 2015 |
Comparative Analysis of OpenCL vs. HDL with Image-Processing Kernels on Stratix-V FPGA |
K. Hill, S. Craciun, A. George, H. Lam |
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| 2015 |
CSP Hybrid Space Computing for STP-H5/ISEM on ISS |
C. Wilson, A. George, et al. |
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| 2015 |
Memory-Aware Optimization of FPGA-based Space Systems |
N. Wulf, A. George, A. Gordon-Ross |
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| 2015 |
Performance and Productivity Evaluation of Hybrid-Threading HLS versus HDLs |
G. Wang, H. Lam, A. George, G. Edwards |
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| 2015 |
In-System Testing of Xilinx 7-Series FPGAs: Part 1-Logic |
H. Modi, P. Athanas |
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| 2015 |
Low-level PGAS computing on many-core processors with TSHMEM |
B. Lam, A. George, H. Lam, V. Aggarwal |
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| 2015 |
Discovering Reusable Hardware Using Birthmarking Techniques |
K. Zang, P. Athanas |
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| 2015 |
A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applications |
A. Shastri, G. Stitt, and E. Riccio |
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| 2015 |
Low-Overhead FPGA Middleware for Application Portability and Productivity |
R. Kirchgessner, A. George, G. Stitt |
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| 2015 |
CMT-bone: A Mini-App for Compressible Multiphase Turbulence Simulation Software |
Kumar, Nalini, Mrugesh Sringarpure, Tania Banerjee, Jason Hackl, S. Balachandar, Herman Lam, Alan George, and Sanjay Ranka |
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| 2014 |
Comparative Analysis of Present and Future Space Processors with Device Metrics |
T. M. Lovelly, K. Cheng, W. Garcia, and A. D. George |
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| 2014 |
CSP: A Multifaceted Hybrid System for Space Computing |
P. Gauvin, J Urriste, D. Rudolph, J. Stewart, C. Wilson, C. Morales, A. George, H. Lam, A. Stoddard, A. Wilson, M. Wirthlin, G. Crum |
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| 2014 |
CSP: A Multifaceted Hybrid Architecture for Space Computing |
D. Rudolph, C. Wilson, J. Stewart, P. Gauvin, A. D. George, H. Lam, G. Crum, M. Wirthlin, A. Wilson, and A. Stoddard |
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| 2014 |
Simulative analysis of a multidimensional torus-based reconfigurable cluster for molecular dynamics |
A. Lawande, H. Yang, A. George, and H. Lam |
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| 2014 |
CERE: a CachE Recommendation Engine: Efficient Evolutionary Cache Hierarchy Design Space Exploration |
G. Yessin, A. A. Badawy, V. Narayana, D. Mayhew, and T. El-Ghazawi |
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| 2014 |
Symbiotic Scheduling of Concurrent GPU Kernels for Performance and Energy Optimizations |
T. Li, V. K. Narayana and T. El-Ghazawi |
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| 2014 |
New approaches for in-system debug of behaviorally-synthesized FPGA circuits |
Josh Monson and Brad Hutchings |
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| 2014 |
A Method and Case Study on Identifying Physically Adjacent Multiple-Cell Upsets Using 28-nm, Interleaved and SECDED-Protected Arrays |
M. Wirthlin, D. Lee, G. Swift, and H. Quinn |
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