Investigating TI KeyStone II and quad-core ARM Cortex-A53 Architectures for On-board Space Processing

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Year

2017

Authors

B. Schwaller, B. Ramesh, A. George

Additional Citation Information

Proc. of IEEE High-Performance Extreme Computing (HPEC) Conference, Waltham, MA, Sep. 12-14, 2017, doi: 10.1109/HPEC.2017.8091094.