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Using Hard Macros to Reduce FPGA Compilation Time

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FPL10_B1b.pdf
Year
2010
Authors
C. Lavin, M. Padilla, S. Ghosh, B. Nelson, B. Hutchings, and M. Wirthlin
Additional Citation Information
Proc. of International Conference on Field-Programmable Logic and Applications (FPL), Aug. 31 - Sep. 2, 2010